AMD large and small nuclear patent exposure: or used in the next generation of Ryzen CPU and APU

WCCFTech has just exposed an interesting new patent obtained by AMD, because it indicates that the next-generation Ryzen CPU/APU product line may adopt a “small and small core” design concept similar to mobile device platforms. Over the years, smartphone SoC manufacturers have fully verified the big.LITTLE architecture, and Intel plans to test the 16C / 24T core design on the 12th-generation Alder Lake-S desktop product line.

WCCFTech has just exposed an interesting new patent obtained by AMD, because it indicates that the next-generation Ryzen CPU/APU product line may adopt a “small and small core” design concept similar to mobile device platforms. Over the years, smartphone SoC manufacturers have fully verified the big.LITTLE architecture, and Intel plans to test the 16C / 24T core design on the 12th-generation Alder Lake-S desktop product line.

AMD large and small nuclear patent exposure: or used in the next generation of Ryzen CPU and APU

There have been rumors that AMD will transition to a hybrid architecture in the next generation of chip designs, and the newly exposed “Task Transition” patents have more or less confirmed this.

AMD large and small nuclear patent exposure: or used in the next generation of Ryzen CPU and APU

Friends who are familiar with the ARM SoC architecture should not be difficult to understand that big.LITTLE can combine different core IPs to achieve a better balance of performance and energy efficiency.

AMD large and small nuclear patent exposure: or used in the next generation of Ryzen CPU and APU

Intel’s 12th-generation x86 processor (Lakefield SoC) also managed to combine the high-performance Core Cove core with the low-power Atom Gracemont core.

AMD large and small nuclear patent exposure: or used in the next generation of Ryzen CPU and APU

Although it has not been widely adopted, as Intel and AMD lead the transformation in next-generation chip design, system and software developers will soon follow up early testing.

AMD large and small nuclear patent exposure: or used in the next generation of Ryzen CPU and APU

Closer to home, AMD submitted this interesting heterogeneous design patent in December 2019, and the company has already achieved the goal of “converging two different chip IPs in the same package” on the APU product line.

According to the documentation of the new patent, AMD describes a unique method, system, and device that can compare performance metrics with associated thresholds, or use other indicators to determine whether multiple tasks should be transferred from a certain set of CPU cores. To another group.

AMD large and small nuclear patent exposure: or used in the next generation of Ryzen CPU and APU

In the process of workload migration, it is obvious that specific adjustments need to be made to the related tasks of the two sets of CPUs. For example, while suspending the task of the source CPU core, it is also necessary to refer to the status information of the target CPU core so that it is ready to undertake the load transfer.

As we all know, heterogeneous architectures tend to use large cores for high-performance workloads, while small cores are more suitable for efficiency-optimized multi-threaded tasks.

The new patent indicates that AMD will communicate between two sets of CPU cores through the same interconnected chiplet, while granting internal communication permissions to share information such as core utilization, memory usage/access, and energy consumption in idle/load states.

AMD large and small nuclear patent exposure: or used in the next generation of Ryzen CPU and APU

Finally, there are rumors that AMD will use the Zen 5 large core + Zen 4D small core design on the Strix Point APU chip, but they will not see you until 2024.

At the same time, with the debut of Intel’s Alder Lake chip later this year, it is expected that the latest version of the Windows operating system will also implement a large number of updates to support the hybrid architecture and new scheduling optimization procedures.

As for whether the heterogeneous architecture can deliver a satisfactory answer to the majority of consumers on the x86 mainstream platform, it remains to be tested.

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