Design of keyboard interface circuit based on complex programmable logic device

The reactive power compensation device is a device used to compensate the shortage of reactive power in the grid, improve the power factor, ensure the safe operation of the power supply system and save electric energy, and its core is the controller. This controller integrates reactive power compensation, power metering, power quality monitoring and communication. It samples and calculates power grid parameters in real time and displays them on the LCD. It can also set system parameters through the keyboard to change the parameters. The operating mode of the controller, etc.

1 Introduction

The reactive power compensation device is a device used to compensate the shortage of reactive power in the grid, improve the power factor, ensure the safe operation of the power supply system and save electric energy, and its core is the controller. This controller integrates reactive power compensation, power metering, power quality monitoring and communication. It samples and calculates power grid parameters in real time and displays them on the LCD. It can also set system parameters through the keyboard to change the parameters. The operating mode of the controller, etc.

The minimum system of the controller is composed of MCU 80C196KC and programmable MCU peripheral interface chip PSD834F2, which saves some small-scale chips such as address latches and decoders, simplifies the hardware circuit, and improves the reliability of the system. sex. The programs, data and parameters required for system operation are placed in PSD834F2. Replacing some digital devices to expand the peripheral circuits of the system with complex programmable logic devices (CPLDs) further improves the performance of the system and facilitates debugging and maintenance. The following will specifically introduce how to use CPLD to expand the keyboard and Display circuit.

2 Hardware Design of Keyboard Input Module

The keyboard input is mainly used for the on-site current transformation ratio, the number of capacitor groups, the capacity of a single group of capacitors, the upper and lower voltage limits, the upper limit of harmonics, the address number of the controller and other system parameters. And cooperate with the display module to check the voltage, current, reactive power, active power, power factor, etc. of each phase.

When designing the keyboard, if the software scanning method is adopted, although the hardware circuit is simple, the scanning will consume a lot of time of the CPU and reduce the overall performance of the system; if the interface chip 8279 is used to manage the keyboard, it can replace the CPU to complete the control of the keyboard. , to reduce the burden on the CPU, but the 8279 is bulky and has a single function. Therefore, the system uses a complex programmable logic device (CPLD) to design the interface circuit of the keyboard to complete the scanning of the keyboard. When a key is pressed, an interrupt signal is generated for the CPU to read the scan code. In addition, CPLD can also realize the interface circuit of other modules and complete functions such as address decoding.

The system adopts 4X4 keyboard, and its hardware circuit is shown in Figure 1:

Design of keyboard interface circuit based on complex programmable logic device

Figure 1 4X4 keyboard block diagram

The CPLD uses Lattice’s ispLSI1016E-100L device, which includes 32 I/O pins, 4 dedicated pins, an integration density of 2000 PLD equivalent gates, a pin-to-pin delay of 7.5ns, and an operating frequency of 7.5 ns. is 100MHz. The device consists of a lumped routing area (GRP) and a universal logic block (GLB), and the GLBs are connected through the GRP.[page]

There are many ways to describe the internal logic functions of complex programmable logic devices (CPLDs). This system adopts the combination of schematic diagram input and VHDL language description, which can give full play to the advantages of both and speed up the development process. Hierarchical design is adopted in the design, and the top layer describing the overall function of the system is input by using the schematic diagram, and some functional modules in the schematic diagram are written in VHDL. The actual schematic diagram is shown in Figure 2:

Design of keyboard interface circuit based on complex programmable logic device

Figure 2 The actual schematic diagram of the keyboard logic

The Module 1 module in the above figure realizes the frequency division function. CLK comes from the CLKOUT pin of the microcontroller 80C196KC, its cycle is 3 clock oscillation cycles, and the duty cycle is 33%. If the single-chip microcomputer uses a 16M crystal oscillator, its frequency is about: 16M/3=5.33M. Module 1 reduces the frequency to about 1K, and Module 2 makes O3~O0 output low level in sequence at one-second intervals to scan the keyboard. When a key is pressed, one of I3~I0 is low level, the exclusive OR gate outputs a high level pulse, latches the keyboard state and applies for an interrupt to the microcontroller. The address space allocated by the system for the keyboard is 0xf100~0xf1ff, and the scan code of the keyboard can be read within this range.

Due to limited space, only the VHDL statements of Module 2 are given below, as follows:

LIBRARY ieee;

USE ieee.STd_logic_1164.ALL;

USE ieee.std_logic_unsigned.ALL;

ENTITY Module2 IS

PORT DD defines the port

( clk : IN std_logic;

q : OUT std_logic_vector (3 DOWNTO 0)

);

END Module2;

ARCHITECTURE Module2 of Module2 IS

BEGIN

PROCESS (clk)

VARIBLE sum: integer:=0; DD defines the variable sum, the initial value is 0

BEGIN

IF (clk’event AND clk=’1′) THEN

sum:=sum+1; when DDclk is a rising edge, add 1 to sum

IF (sum”=5) THEN

sum:=1;

END IF;

END IF;

CASE sum IS DD outputs the corresponding value according to sum

WHEN 1 = “q” = “1110”;

WHEN 2 = “q” = “1101”;

WHEN 3 = “q” = “1011”;

WHEN 4 = “q” = “0111”;

WHEN THERS = “q” = “1111”;

END CASE;

END PROCESS;

END Module2;[page]

3 Correspondence between keyboard scan codes and corresponding keys

The interrupt service routine reads the scan code in the register FD18, and after judgment, it can know which key is pressed, and then transfer to the corresponding program for processing. The specific correspondence between key numbers and scan codes is shown in Table 1:

Table 1 Key number and scan code correspondence table

Design of keyboard interface circuit based on complex programmable logic device

4 Software design of keyboard input module

Some basic parameters of the system can be set or changed through the keyboard. Each time a key is pressed, the CPLD will apply for an interrupt to the CPU after scanning the key value. After the CPU enters the keyboard management interrupt program, it reads and stores the key value and sets the received key value flag. The main program recognizes the flag and processes the received key value.

The parameter setting format is: A**B**…*B. That is to say, press the ‘A’ key to enter the setting state, the combination of ‘**’ indicates the setting item, ‘B’ confirms the setting item, the value of the item set by ‘**…*’, and the last ‘B’ is the terminator , indicating the end of this setting. The software processing flow of the setting steps is shown in Figure 3:

Design of keyboard interface circuit based on complex programmable logic device

Figure 3 Process flow chart of system parameter setting

5 Conclusion

The keyboard interface extended with complex programmable logic device (CPLD) is practical and effective, which not only improves the response speed of the single-chip microcomputer, but also simplifies the hardware circuit. In addition, CPLDs can also be used in other interface designs to further reflect their performance.

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