# Realization and design of IIR digital filter based on cascade structure and VHDL language on FPGA

IIR digital filters have broad applications in many fields. Compared with the FIR digital filter, it can obtain high selectivity with a lower order, uses less memory cells, is economical and high in efficiency, and can provide better out-of-band attenuation characteristics under the same gate-level scale and the same clock speed . The following introduces a method of implementing IIR digital filters on FPGA.

IIR digital filters have broad applications in many fields. Compared with the FIR digital filter, it can obtain high selectivity with a lower order, uses less memory cells, is economical and high in efficiency, and can provide better out-of-band attenuation characteristics under the same gate-level scale and the same clock speed . The following introduces a method of implementing IIR digital filters on FPGA.

The structure of the IIR digital filter The IIR filter of any order can be decomposed by mathematics, expressed as:

In this way, an IIR filter of any order can be cascaded through a number of second-order networks (also called the second-order basic section of the filter), and its structure is shown in Figure 1. Among them, represents the second-order network of the i-th level.

For each second-order basic section, it can be realized by transposing the direct type II structure, as shown in Figure 2.

The advantage of adopting this cascade structure to realize the IIR filter is that each basic section is only related to a certain pair of poles and a pair of zeros of the filter, the adjustment coefficients a0i, a1i, a2i, only the i-th pair of the filter is adjusted individually The zero point does not affect any other zeros and poles. Similarly, adjusting the b1i and b2i coefficients also individually adjusts the i-th pair of poles. Therefore, this structure facilitates the accurate realization of the zeros and poles of the filter, and also facilitates the adjustment of the frequency response performance of the filter. Another advantage of this structure is that fewer storage units are required. When hardware is implemented, a second-level section can be used for time-division multiplexing, thereby reducing the requirement for FPGA hardware resources.[Page]

Design of IIR digital filter

Using the filter design and analysis tool (EDATool) in the MATLAB signal processing toolbox can easily design an unquantified IIR filter that meets the application requirements. It is necessary to further decompose and quantify the IIR filter designed by MATLAB to obtain the filter coefficients that can be implemented with FPGA.

Due to the cascade structure, how to combine each pole and zero of the filter so as to minimize the noise contained in the output of the digital filter is a very critical issue. In order to produce the optimal quantized IIR digital filter, the following steps are used to design:

First calculate the poles and zeros of the overall transfer function;

Select the pole with the largest amplitude and the zero point closest to it, and use them to form a second-order basic node transfer function;

For the remaining poles and zeros, follow the steps similar to (2) until all second-order basic nodes are formed.

The design carried out by the above three-step method can ensure that the quantization rounding error generated by the N-bit multiplier in the IIR digital filter is minimized. In order to design a digital filter that can be implemented with FPGA, it is necessary to quantize the filter coefficients of the second-order basic section obtained by decomposition in the previous step, that is, to express it with a fixed word length. In the quantization process, there are different degrees of quantization errors, which will cause the frequency response of the filter to deviate, and in severe cases, the pole of the IIR filter will move outside the unit circle, and the system will lose stability. In order to obtain the optimal filter coefficients, the following steps are used for quantization:

Calculate the absolute value of each coefficient;

Find the maximum value in the absolute value of each coefficient;

Calculate the smallest integer greater than this absolute value;

Reverse the result of (3) to obtain a negative integer;

Calculate the minimum number of digits required to represent this integer;

Calculate the remaining digits used to represent the fractional part of the coefficient value.

In addition to the quantization error of the coefficients, the finite word length effect in the digital filter calculation process will also cause errors. Therefore, the data width of the multiplier, adder and register in the filter must also be designed reasonably to prevent the phenomenon of limit cycles and Overflow oscillation.

VHDL description of IIR digital filter

The IIR digital filter designed in the previous section can be further described in VHDL language, and can be implemented on FPGA after compilation, functional simulation, synthesis and timing simulation. Due to the cascade structure, the VHDL description of each second-order basic section is similar, but the coefficients of the filter are different. The following focuses on the VHDL description of the second-order basic section.

The top-level structure of the second-order basic section described in VHDL is shown in Figure 3. The data is processed in the execution unit. The execution unit contains arithmetic and logic units and some registers; the arithmetic and logic units are mainly composed of serial multipliers and accumulators; the memory includes two parts of working RAM and coefficient ROM, which are used to store the intermediate results of the calculation and the coefficients of the filter. ; The memory and the execution unit are connected by an internal bus; the control module includes a program ROM and a program control unit. The program ROM stores a filter algorithm program. The program control unit is used to interpret instructions and generate control signals for the data processing module.

This structure can receive either serially input data or parallel input data, which can be set through SEL. The external CPU can access the calculation results of the filter through the READ signal. In addition, the external CPU can also access the internal memory through the address bus A[3:0]and use the WRITE signal to write the filter coefficients, so that the external CPU You can configure the filter according to your own needs and realize various functions flexibly. The meaning of each signal is as follows:

CLK: system clock;

RES: asynchronous global reset signal, low effective;

SDATA: serial input data;

PDATA: Parallel input data;

SEL: Set the input data to be parallel or serial;

WRITE: write signal, low effective;

SRES: Synchronous reset signal, high effective;

CLKI: external CPU clock;

A[3:0]: External CPU accesses the address bus of internal registers;

OUT: Output data.

The internal arithmetic and logic unit is the core of the entire filter, and its structure is shown in Figure 4.

The calculation process is that X and Y are input data, enter the multiplier through the selector, the arithmetic and logic unit reads the coefficient of the filter from the coefficient ROM to multiply the input data, and the result of the multiplication is added to the result of the previous step Enter the accumulator, the accumulator reads the intermediate result A calculated in the previous step and calculates, and finally stores the result M of this step calculation in RAM.

Concluding remarks

This article introduces a method to implement IIR digital filter on FPGA with cascade structure. In actual use, the IIR filter can be easily modified to meet different index requirements according to different accuracy requirements, and flexibly form different types of filters of any order. At the same time, during system operation, the external CPU can flexibly modify the filter coefficients and change the frequency response of the filter to meet specific application requirements.