Although most of the discussion about chip manufacturing has focused on the cutting-edge and extremely fast and complex aspects of the industry, the demand for “traditional” process technology is now higher than ever, and the number is also higher than the latest and greatest. Much larger. These traditional processes constitute the backbone of most modern Electronic products, so it is usually a win-win for manufacturers and chip designers to provide the same technology at a lower cost/power consumption.
To this end, Samsung announced the launch of a new 17-nanometer process node, designed for customers who are still using planar 28-nanometer process but want to use 14-nanometer FinFET technology.
In modern processor design, the manufacturing process node has a set of design rules. To design a chip on this node, it must follow these design rules. Usually these rules have absolute worst-case restrictions, but if chip designers can use these restrictions to optimize their products, it is good to be familiar with what can or cannot be done.
Therefore, a process that uses planar transistors like Samsung’s 28nm will have a set of 14nm design rules different from Samsung’s use of 3D FinFET transistors. The design rules also consider where to place the power supply, connectivity, and metal stacking from the transistor to the contact pads used for the package.
In terms of manufacturing, at a high level, there are two or three main parts to consider. The front end of the production line (FEOL) is the starting point for circuit manufacturing and transistor design. When we talk about cutting-edge technology, it is the FEOL part of the inner application, because we need better and better tools to make smaller and smaller details in silicon to get the best transistors. Once FEOL has completed many layers with transistors, the wafer will move to the back-of-line (BEOL) for the rest of the circuit-BEOL is responsible for placing the connection layer, power layer and all auxiliary connections. After BEOL, the chip will be tested, diced (diced) and packaged.
Sometimes the term middle line or middle end of line (MEOL) is used for chips with through silicon vias (TSV) designed for multi-chip stacking.
At the overall level, FEOL and BEOL at any process node (such as 28nm) have design rules for the 28nm version of these two market segments. Sometimes manufacturers will combine a set of design rules on FEOL with another set of design rules on BEOL to produce a new product line with some of the functions of both. This is what Samsung is doing with the new 17nm / 17LPV (Low Power Value) process announced at the Samsung Foundry Forum.
17LPV will be combined with 14nm FEOL, effectively connecting 14nm FinFET transistors with 28nm BEOL. This means that customers can obtain the performance/power advantages of FinFET designs at an additional cost, without having to pay the additional cost of a higher density BEOL. In the end, the chip size may still be determined by the larger node BEOL, but it seems that lower power transistors are required.
Samsung claims that compared with the traditional 28-nanometer process, the 17LPV chip area will be reduced by more than 43%, the performance will be improved by 39%, or the power efficiency will be improved by 49%.
The first application of 17LPV will be a camera image signal processor as part of Samsung’s CMOS image sensor product portfolio. These chips do not necessarily need density, which makes 17LPV very suitable, but optimized power and cost will benefit the expertise involved in stacking.
In addition, Samsung is integrating 17LPV into its high-voltage products for DDIC/Display drivers that require back-end high-voltage support combined with improved logic.
In addition to 17LPV, Samsung foundries are creating 14LPU (we think this is still 28nm BEOL + 14nm FEOL) or Low Power Ultimate for embedded MRAM and microcontrollers.
The exact time scale of this new node has not yet been disclosed, although representatives from Samsung foundries have called this node part of a “paradigm shift” within the company when developing new professional process solutions for these markets.
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